ECE/CS 752 F2017 Readings for Midterm 1

Last Updated: 9/8/2017

This reading list may be updated at any time prior to the exam review.

Key for Locations

NOTE:Most IEEE and ACM journal articles can be located online through the UW library portal. Papers are directly linked below.

Introduction & Technology Challenges

·        Shen & Lipasti, Chapter 1.

·        Read by 9/11/17: 2015 ITRS Update [PDF] (other). Read Section 1, 5, 6, 8, 9, and skim the rest.

·        Read by 9/11/17: Shekhar Borkar, “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation,” IEEE Micro 2005, November/December 2005 (Vol. 25, No. 6) pp. 10-16. Online PDF

·        Review by 9/13/17:Jacobson, H, et al., “Stretching the limits of clock-gating efficiency in server-class processors,” in Proceedings of HPCA-11, 2005.  Online PDF

Pipelining

·        Shen & Lipasti, Chapter 2.

·        Watch online review lectures from ECE 552.

·        Read by 9/13/17: J. E. Smith. An Analysis of Pipeline Clocking, University of Wisconsin-Madison ECE Unpublished Note, March 1990. URL: http://ece752.ece.wisc.edu/papers/clocks.pdf (web).

Superscalar Processors

·        Shen & Lipasti Chapter 4, 5, 9

·        Read by 9/15/2017: J. E. Smith. A Study of Branch Prediction Strategies, Proceedings of the 8th Annual Symposium on Computer Architecture, pp. 135-148, May 1981 (B4).

·        Read by 9/18/2017: T-Y. Yeh and Y. Patt. Two-level Adaptive Training Branch Prediction, Proc. 24th Annual International Symposium on Microarchitecture, Nov 1991 (B4).

·        Read by 9/20/2017: D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo. The IBM System/360 model 91: Machine Philosophy and Instruction-Handling, IBM Journal of Research and Development, Jan. 1967 (B4).

·        Read by 9/22/2017: J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. on Computers, May 1988 (B4).

·        Read by 9/25/2017: Y. N. Patt, W. W. Hwu, and M Shebanow. HPS, a New Microarchitecture: Rationale and introduction, Proceedings of the 18th Workshop on Microprogramming, Pacific Grove, CA, pp. 103-108, Dec. 1985 (B4).

·        Read by 9/27/2017: Gurindar S. Sohi and S. Vajapeyam. Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, Proc. 14th Annual Symposium in Computer Architecture, June 1987 (B4)

·        Review by 10/2/2017: Borch, E., Tune, E., Manne, S., and Emer, J. Loose Loops Sink Chips. In Proceedings of HPCA-8, Feb. 2003.

Case Studies

·        Shen & Lipasti Chapter 6-7 (read), 8 (skim)

·        Read by 10/4/2017: G. F. Grohoski. Machine Organization of the IBM RISC System/6000 Processor, IBM Journal of Research and Development, 34(1):37-58, 1990 (B4).

·        Read by 10/6/2017: Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor, IEEE Micro, April 1996 (B4).

·        Review by 10/9/2017: K. Czechowski, V. Lee, E. Grochowski, R. Ronen, R. Singhal, R. Vuduc, P. Dubey. Improving the Energy Efficiency of Big Cores. Proceeding of ISCA-14, June 2014.